Compatible SLE4428 Card, Compatible SLE5528 Card, ISSI4428 Card, IS23SC4428 Card.
1-KBYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY CODE (PSC)
• Standard CMOS process
• 1024 x 8 bits EEPROM organization
• Byte-wise addressing
• Byte-wise erase/write
• Irreversible byte-wise write protection
• Single 5V power supply for read and write/erase
• Low power operation:
– 3 mA typical active current
• 5 ms programming time
• 3-wire serial interface
• 20 KHz serial clock rate
• Contact configuration and serial interface, ISO standard 7816 (Synchronous Transmission) compatible.
• High ESD protection: > 4 KV
• High reliability:
– 1,000,000 erase/write cycles guaranteed
– 10 years data retention
• Wide operating temperature range – 0 to +70°C Commercial; –40 to +85°C Industrial
Additional feature of IS23SC4428:
• 2-byte Programmable Security Code (PSC) for memory write/erase protection
IS23SC4418 contains 1024 x 8 bits of EEPROM with programmable write protection for each byte. Random read access to any byte in the memory is always possible. The memory can also be erased and written byte by byte. Erasing old data in the byte location must be performed before new data can be written to the location. Each byte in the memory has a corresponding protect bit. The protect bits are only one-time programmable and cannot be erased. After the protect bits are enabled (logic 0), the corresponding bytes can never be changed again. A write-protect bit with data-compare function is available for user to verify the data in the memory before enabling the protect bit.
IS23SC4428 offers all the features in IS23SC4418. In addition, it offers two bytes of Programmable Security Code (PSC) against unauthorized memory write/erase operations. All the memory, except for the PSC can always be read, but the memory can be written or erased only after PSC verification. If the user fails to enter the correct PSC in eight consecutive attempts, the device will block any further PSC entry attempts and the memory can never be erased or written again.
The PSC bytes are pre-programmed by the manufacturer with a code, which is specified for the customer for device transport security purposes, before the devices are shipped to the customer. The Error Counter will be pre-erased by the manufacturer to allow maximum attempts (maximum of eight) for PSC entry.
Read 8-Bits Data
The read 8-bit data command allows the user to specify the address (A0-A9) of the data byte to be read from the device. The byte address for the next output data is automatically incremented after every eight clock pulses. The data is output in sequential order, with the data from address n followed by the data from address n+1.
Read 9-Bits Data with Protect Bit
The read 9-bit data command operates similarly to read 8-bit data command except that the protect bit for each byte is output after each 8-bit data and the address for the next output data is incremented after every nine clock pulses.
Write/Erase Data Byte without Protect Bit
The write/erase data byte without protect bit command writes the new data into the specified byte location. There are three kinds of write/erase operations which are automatically executed by the device:
1. Erase and subsequent write if 203 clock pulses at f < 20 KHz are applied. (See Figure 8.)
2. Write only if 103 clock pulses at f < 20 KHz are applied. This operation is only suitable if single bits of one byte shall be changed only from 1 to 0.
3. Erase only if the input data = FFH and 103 clock pulses at f < 20 KHz are applied. (See Figure 9.)
Note: Erase means 0 → 1. Write means 1 → 0.
If the protect bit of the corresponding byte location is
enabled, the write/erase operation will have no effect on
Write/Erase Data Byte with Protect Bit
The write/erase data byte with protect bit command operates similarly to the write/erase data bytewith protect bit command except that it also writes 0 to the
corresponding protect bit. After the protect bit is set to 0 (write protection enabled), it cannot be changed again.
Write Protect Bit with Data Comparison
The write protect bit with data comparison command writes 0 to the corresponding protect bit only if the input data and the data in the specified memory location are the same. After the protect bit is set to 0 (write protection enabled), it cannot be changed again. The execution of write/erase commands are terminated after a given number of clock cycles. When the operation is done, the device will bring the I/O state to 0. Only RST transition from 0 to 1 can set the I/O state back to 1.
IS23SC4428 SECURITY FEATURES
Without entering Programmable Security Code (PSC), only memory read access is possible. However, the content of the PSC addresses (1022 and 1023) cannot be read out. If reading PSC is attempted, 00H will be output. The PSC verification procedure must be performed in the following sequence:
1. Write one to not-written Error Counter bit, address 1021
2. Enter first PSC byte, address 1022
3. Enter second PSC byte, address 1023
4. After successful PSC verification, the Error Counter should be erased to reactivate the 8 PSC entry attempts. If the PSC entry is incorrect, go back to step 1. If all the Error Counter bits have been written, any further PSC entry will be blocked and the memory can never be changed again.
Writing Error Counter
The number of erased bits (logic 1) in Error Counter determines the number of possible attempts (maximum of eight). Before PSC entry, only writing of error counter is possible. After PSC is successfully verified, the counter can now be erased. Before disconnecting the supply voltage Vcc, the counter should be erased in order to reactivate the eight attempts.
Entry of PSC
The least significant PSC byte beginning with the least significant bit must be entered first and then the most significant. If both PSC byte 1′s and byte 2′s comparisons prove correct, the memory erase/write access will be enabled and PSC may be changed as wished, except the corresponding protect bits are 0 (enabled).
Condition when supplied
IS23SC4428 is supplied by the manufacturer with a 2-byte PSC (transport security code) which is determined in cooperation with the customer.